1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device including a gate electrode having a silicide film and a method of fabricating the same.
2. Description of the Background Art
In general, elements are increasingly refined, improved in density, increased in speed and reduced in power consumption in the field of LSIs (large-scale integrated circuits).
In order to refine an element, it is necessary to reduce the resistance values of a gate electrode and source/drain regions of a MOS transistor and a wire for inhibiting the resistance values from increase following the refinement. A method of forming a silicide film on a polysilicon layer constituting the gate electrode and the wire as well as the source/drain regions formed on a silicon substrate is known as one of methods of reducing the resistance values of the gate electrode, the source/drain regions and the wire. The resistance values of the gate electrode and the wire consisting of polysilicon and the source/drain regions formed on the silicon substrate can be reduced due to the silicide, which is a compound of silicon and a metal having a lower resistance value than silicon.
A salicide (self-aligned silicide) process of forming a silicide film on a polysilicon layer constituting a gate electrode and source/drain regions located on the surface of a silicon substrate in a self-aligned manner has generally been developed as a method of forming a silicide film. This salicide process is disclosed in Japanese Patent Laying-Open No. 2000-22150, for example. According to this salicide process capable of silicifying the gate electrode and the source/drain regions through the same step, the number of fabrication steps and the fabrication cost can be reduced. Therefore, the salicide process is widely employed for a process of fabricating a MOS transistor.
In a structure including a MOS transistor formed through the aforementioned salicide process, the resistance can be reduced due to the silicide film and hence the resistance can be inhibited from increase also when the MOS transistor is refined. When the MOS transistor is refined, however, the distance between the gate electrode and a wire adjacent thereto is reduced to disadvantageously increase the capacitance between the gate electrode and the wire. If the center distance between the gate electrode and the wire remains intact, the capacitance therebetween can be reduced by reducing the line widths of the gate electrode and the wire thereby increasing the distance between the side surfaces of the gate electrode and the wire. If the line widths of the gate electrode and the wire are excessively reduced, however, the width of the silicide film is also excessively reduced to disadvantageously abruptly increase the resistance due to a thin-line effect of the silicide film.